High throughput bandwidth optimized VLSI design for motion compensation in AVS HDTV decoder

In this paper we present a motion compensation （MC） design for the newest Audio Video coding Standard （AVS） of China. Because of compression-efficient techniques of variable block size （VBS） and sub-pixel interpolation, intensive pixel calculation and huge memory access are required. We propose a parallel serial filtering mixed luma interpolation data flow and a three-stage multiplication free chroma interpolation scheme. Compared to the conventional designs, the integrated architecture supports about 2.7 times filtering throughput. The proposed MC design utilizes Vertical Z processing order for reference data re-use and saves up to 30% memory bandwidth. The whole design requires 44.3k gates when synthesized at 108 MHz clock frequency using 0.18-μm CMOS technology and can support up to 1920×1088@30 fps AVS HDTV video decoding.     

A parallel memory architecture for video coding

To efficiently exploit the performance of single instruction multiple data （SIMD） architectures for video coding, a parallel memory architecture with power-of-two memory modules is proposed. It employs two novel skewing schemes to provide conflict-free access to adjacent elements （8-bit and 16-bit data types） or with power-of-two intervals in both horizontal and vertical directions, which were not possible in previous parallel memory architectures. Area consumptions and delay estimations are given respectively with 4, 8 and 16 memory modules. Under a 0.18-pm CMOS technology, the synthesis results show that the proposed system can achieve 230 MHz clock frequency with 16 memory modules at the cost of 19k gates when read and write latencies are 3 and 2 clock cycles, respectively. We implement the proposed parallel memory architecture on a video signal processor （VSP）. The results show that VSP enhanced with the proposed architecture achieves 1.28× speedups for H.264 real-time decoding.     

A fast motion estimation algorithm for mobile communications

The limitation of processing power, battery life and memory capacity of portable terminals requires reducing encoding complexity in mobile communications. Motion estimation (ME) is the most computationally intensive module in a typical video codec, which determines not only the encoder’s performance but also the reconstructed video quality. In this paper, a fast ME algorithm for H.264/AVC baseline profile coding is proposed based on the analysis of motion vector field and error surface, and the statistical distributions of different type macroblocks (MBs). Simulation results showed that: in comparison with MVFAST, the proposed algorithm can decrease the computational load over 7.2% with no requirement of expanding memory capacity while maintaining the same video quality as MVFAST. Furthermore, its simplicity makes it easy to be implemented on hardware.     

A fast motion estimation algorithm for mobile communications

The limitation of processing power, battery life and memory capacity of portable terminals requires reducing encoding complexity in mobile communications. Motion estimation (ME) is the most computationally intensive module in a typical video codec, which determines not only the encoder's performance but also the reconstructed video quality. In this paper, a fast ME algorithm for H.264/AVC baseline profile coding is proposed based on the analysis of motion vector field and error surface, and the statistical distributions of different type macroblocks (MBs). Simulation results showed that: in comparison with MVFAST, the proposed algorithm can decrease the computational load over 7.2% with no requirement of expanding memory capacity while maintaining the same video quality as MVFAST. Furthermore, its simplicity makes it easy to be implemented on hardware.     

Efficient video downscaling transcoder from MPEG-2 to H.264

The new H.264 video coding standard achieves significantly higher compression performance than MPEG-2. As the MPEG-2 is popular in digital TV, DVD, etc., bandwidth or memory space can be saved by transcoding those streams into H.264 in these applications. Unfortunately, the huge complexity keeps transcoding from being widely used in practical applications. This paper proposes an efficient transcoding architecture with a smart downscaling decoder and a fast mode decision algorithm. Using the proposed architecture, huge buffering memory space is saved and the transcoding complexity is reduced. Performance of the proposed fast mode decision algorithm is validated by experiments.     

Blocking optimized SIMD tree search on modern processors

Tree search is a widely used fundamental algorithm. Modern processors provide tremendous computing power by integrating multiple cores, each with a vector processing unit. This paper reviews some studies on exploiting single instruction multiple date (SIMD) capacity of processors to improve the performance of tree search, and proposes several improvement methods on reported SIMD tree search algorithms. Based on blocking tree structure, blocking for memory alignment and dynamic blocking prefetch are proposed to optimize the overhead of memory access. Furthermore, as a way of non-linear loop unrolling, the search branch unwinding shows that the number of branches can exceed the data width of SIMD instructions in the SIMD search algorithm. The experiments suggest that blocking optimized SIMD tree search algorithm can achieve 1.6 times response speed faster than the un-optimized algorithm.     

一种具有可分级转码能力的空时OFDM视频传输方法

结合空时OFDM和转换编码技术,提出了一种无线衰落信道下具有可分级转码能力的鲁棒视频传输方法.采用可分级转码器将高质量的MPEG-2压缩视频转换为低码率、低分辨率MPEG-4可分级码流来满足网络带宽和终端设备显示的要求.在接收端采用一种层干扰抑制算法,使得分层空时OFDM系统不同层的传输性能存在差异,从而使系统具有不对等保护能力.根据分级码流的重要程度不同,将转码输出的可分级码流分别由分层空时编码OFDM系统的不同层来实现视频的鲁棒传输.实验结果表明:在典型的随机突发错误的无线环境下,提出的具有可分级转码能力的系统的视频传输性能优于传统的非分级转码的视频传输系统.     

基于特征提取的视频预处理方法

针对现有视频识别算法对不同帧中同一对象反复分类、反复识别问题,提出一种基于特征匹配的预处理算法。该算法将前一帧中已识别物体的图像特征与下一帧画面提取出的特征相比较,找出下一帧中已经被分类或识别过的物体,并将其剔除,达到压缩输入视频画面尺寸、提升视频处理效率的目的。为了验证算法的预处理效果,对两组道路图形进行实验,结果表明,该算法平均降低85%的画面尺寸,视频画面处理时间平均降低5%。     

智能传感器电力监测系统接口研究

为了实时研究三相交流电的性能和特征参数,提出基于单片机AT89C52的电力智能传感器监测粗信号处理系统,分析了电力智能传感器监测系统组成,对系统接口电路进行了设计,编写了串行通信软件.仿真实验结果表明,Visual C++6.0上编写的通信软件基本能实现单片机与PC机的数据传输,为电力智能传感器各种粗信号处理做好了准备.     

Highly parallel implementation of sub-pixel interpolation for AVS HDTV decoder

In this paper, we propose an effective VLS1 architecture of sub-pixel interpolation for motion compensation in the AVS HDTV decoder. To utilize the similar arithmetical operations of 15 luma sub-pixel positions, three types of interpolation filters are proposed. A simplified multiplier is presented due to the limited range of input in the chroma interpolation process. To improve the processing throughput, a parallel and pipelined computing architecture is adopted. The simulation results show that the proposed hardware implementation can satisfy the real-time constraint for the AVS HDTV （1 920× 1 088） 30 fps decoder by operating at 108 MHz with 38.18k logic gates. Meanwhile, it costs only 216 cycles to accomplish one macroblock, which means the B frame sub-pixel interpolation can be realized by using only one set of the proposed architecture under real-time constraints.     

射频门禁控制器的设计与实现

设计的射频门禁控制器以AT89C52单片机为核心,以AT24C1024芯片为存储器,通过nRF905SE无线射频收发模块,与总控制器实现无线通信．该设计可以满足与上位机通信、现场门控、门禁控制、考勤等功能的需要．实际运行表明,该射频门禁控制器具备门禁监视系统要求的基本功能,并且具有成本低、性能稳定、可靠和低功耗等优点．     

Efficient VLSI architecture of CAVLC decoder with power optimized

This paper presents an efficient VLSI architecture of the contest-based adaptive variable length code (CAVLC) decoder with power optimized for the H.264/advanced video coding (AVC) standard. In the proposed design, according to the regularity of the codewords, the first one detector is used to solve the low efficiency and high power dissipation problem within the traditional method of table-searching. Considering the relevance of the data used in the process of runbefore’s decoding, arithmetic operation is combined with finite state machine (FSM), which achieves higher decoding efficiency. According to the CAVLC decoding flow, clock gating is employed in the module level and the register level respectively, which reduces 43% of the overall dynamic power dissipation. The proposed design can decode every syntax element in one clock cycle. When the proposed design is synthesized at the clock constraint of 100 MHz, the synthesis result shows that the design costs 11 300 gates under a 0.25 μm CMOS technology, which meets the demand of real time decoding in the H.264/AVC standard.     

Improved fast intra prediction algorithm of H.264/AVC

With advanced prediction modes of intra prediction, intra coding of H.264/AVC offers significant coding gains compared with previous video coding standards. It uses an important tool called Lagrangian rate-distortion optimization (RDO) technique to decide the best coding mode for a block, but the computational burden is extremely high. In this paper, we proposed an improved fast intra prediction algorithm including block type selection and mode decision algorithm based on analysis of edge feature of a block. Our algorithm filters out unlikely block type and candidate modes to reduce the RDO calculations. Experimental results showed that the proposed algorithm can reduce the computation complexity of intra prediction from 52.90% to 56.31%, with 0.04 dB PSNR degradation and 2% increase of bit rate.     

基于流媒体技术的馆藏科技信息视频资源数据库构建

科技信息视频资源是科技情报信息资源不可或缺的重要组成部分。为解决馆藏科技信息视频资源管理不便与利用率不高的问题,按照已建立的资源数字化加工标准要求,对馆藏视频资源进行统一处理,并基于流媒体技术,采用 FMS 流媒体服务器,结合 Flashplayer 在线流媒体开发模式,设计开发了一套 B/S 模式的馆藏科技信息视频资源在线播放数据库系统。该数据库系统投入运行后,馆藏视频资源管理费用降低了约 80%,管理效率提升了约 60%,且视频资源利用率是过去的近 20 倍。同时,也进一步提升了单位科技信息服务质量和影响力。     

多媒体教学中的知识建构

多媒体教学中的知识建构观,主要采纳了建构主义的主动加工信息理论,而主动加工信息的认知机制则是认知的反思或监控。在有效的多媒体教学中,学习者的认知的机制涉及五种基本的认知活动,对教材的直观、概括、具体化以及工作记忆和长时记忆。皮亚杰的建构思想、维果斯基的社会文化理论、布鲁纳的建构观念和激进建构主义等等,都为多媒体教学中知识建构的设计提供了理论依据。     

高职院校数字校园无线视频监控系统设计

分析了高职院校校园中进行视频监控的必要性,对整个视频监控系统的关键技术包括H。264/AVC视频编解码、移动流媒体技术等进行研究,设计了一种应用于手持智能终端的视频监控系统,详细阐述了其体系结构和客户端实现,为高职院校建设数字化校园视频监控提供了一种新的方案。     

Cognitive Architecture and Instructional Design

Cognitive load theory has been designed to provide guidelines intended to assist in the presentation of information in a manner that encourages learner activities that optimize intellectual performance. The theory assumes a limited capacity working memory that includes partially independent subcomponents to deal with auditory/verbal material and visual/2- or 3-dimensional information as well as an effectively unlimited long-term memory, holding schemas that vary in their degree of automation. These structures and functions of human cognitive architecture have been used to design a variety of novel instructional procedures based on the assumption that working memory load should be reduced and schema construction encouraged. This paper reviews the theory and the instructional designs generated by it.     

下一代网络(NGN)中视频监控系统解决方案

实时的视频服务是下一代网络(NGN-Next Generation Network)技术研究的热点之一。传统的网络系统具有异构网络之间的数据交换难度大、可拷性差等特点。基于IMS的网络架构支持固定网络接入需求和未来网络的各种业务需求,并提供对高层多种业务的支持,已经成为下一代网络的发展方向。介绍了IMS,分析基于IMS架构下需要实现的视频监控业务需求,提出了系统设计方案,并对该方案的系统结构与业务应用进行了探讨。     

一种视频会议系统的研究与实现

介绍了使用局域网组播技术和Directshow多媒体开发框架实现多方视频会议系统的方法。系统引入了会议管理服务器以控制多媒体数据在网络中的接入和访问,使网络不会由于多媒体数据的激增而发生拥塞,从而保证服务质量。系统使用了面向对象的方法和UML语言,分析和设计了各个模块。系统的视频部分采用了MPEG-4编解码技术,音频数据留采用了G.729编解码方法。根据该设计方案,完成了该系统的设计和开发,实现了多人同时通讯的模拟视频会议功能。     

A complexity-scalable software-based MPEG-2 video encoder

With the development of general-purpose processors (GPP) and video signal processing algorithms, it is possible to implement a software-based real-time video encoder on GPP, and its low cost and easy upgrade attract developers' interests to transfer video encoding from specialized hardware to more flexible software. In this paper, the encoding structure is set up first to support complexity scalability; then a lot of high performance algorithms are used on the key time-consuming modules in coding process; finally, at programming level, processor characteristics are considered to improve data access efficiency and processing parallelism. Other programming methods such as lookup table are adopted to reduce the computational complexity. Simulation results showed that these ideas could not only improve the global performance of video coding, but also provide great flexibility in complexity regulation.