Optimizing pipeline for a RISC processor with multimedia extension ISA

INTRODUCTION Embedded real-time multimedia applications that involve processing of video and audio streams de- mand an efficient media approach. A thorough survey of media approaches and architectures was given by Dasu and Panchanathan (2002). These media proc- essing architectures can be classified into three cate- gories including dedicated (application-specific) hardware, media processors and instruction set ar- chitecture extensions for general-purpose processors. As for embedded med…

Optimizing pipeline for a RISC processor with multimedia extension ISA

The 32-bit extensible embedded processor RISC3200 originating from an RTL prototype core is intended for low-cost consumer multimedia products. In order to incorporate the reduced instruction set and the multimedia extension instruction set in a unifying pipeline, a scalable super-pipeline technique is adopted. Several other optimization techniques are proposed to boost the frequency and reduce the average CPI of the unifying pipeline. Based on a data flow graph (DFG) with delay information, the critical path of the pipeline stage can be located and shortened. This paper presents a distributed data bypass unit and a centralized pipeline control scheme for achieving lower CPI. Synthesis and simulation showed that the optimization techniques enable RISC3200 to operate at 200 MHz with an average CPI of 1.16. The core was integrated into a media SOC chip taped out in SMIC 0.18-micron technology. Preliminary testing result showed that the processor works well as we expected.