| 用VHDL实现计算机组成原理实验中的RAM存储器系统 |
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| 引用本文： | 朱家兴,付伟.用VHDL实现计算机组成原理实验中的RAM存储器系统[J].蒙自师范高等专科学校学报,2006,4(2):21-23,14. |
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| 作者姓名： | 朱家兴 付伟 |
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| 作者单位： | 红河学院信息科学与电子工程学院 云南蒙自661100 |
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| 摘 要： | 介绍了VHDL硬件描述语言的特点及设计思想,运用VHDL硬件描述语言实现计算机组成原理实验中RAM存储器的设计方法,重点论述了对传统计算机组成原理实验中移植到基于CPLD平台的思路.
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| 关 键 词： | RAM存储器 VHDL CPLD EDA check进程 计算机组成原理 |
| 文章编号： | 1008-9128（2006）02-0021-03 |
| 收稿时间： | 03 7 2006 12:00AM |
| 修稿时间： | 2006-03-07 |
Using VHDL Implementation RAM Memory System of Computer Component Principle Experiment |
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| ZHU Jia-xing,FU Wei.Using VHDL Implementation RAM Memory System of Computer Component Principle Experiment[J].Journal of Mengzi Teachers' College,2006,4(2):21-23,14. |
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| Authors: | ZHU Jia-xing FU Wei |
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| Institution: | College of Information Science and Engineering of Honghe University, Mengzi 661100, China |
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| Abstract: | The characteristic and design idea of VHDL are introduced in this paper.Using the VHDL,we realize the design method of memory element in computer component principle experiment,and the transfer idea basic CPLD platform in traditional computer component principle experiment is discussed especially. |
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| Keywords: | RAM memory element VHDL CPLD EDA check process computer component principle |
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