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| 基于FPGA误码检测仪的建模与设计 | |
| 引用本文： | 郑文斌,黄挚雄,孙晓婷.基于FPGA误码检测仪的建模与设计[J].中国科技信息,2007(18):107-108. |
| 作者姓名： | 郑文斌 黄挚雄 孙晓婷 |
| 作者单位： | 1. 中南大学信息科学与工程学院,410083;福建工程学院,350014 2. 中南大学信息科学与工程学院,410083 3. 福建工程学院,350014 |
| 摘 要： | 提出了一种基于FPGA的误码检测方案，并在FPGA上实现了其功能。该方案不仅提出了锁相环法提取同步信号方法，还纳入了“同步保护”的思想。 |
| 关 键 词： | FPGA 锁相环 同步保护 |
Modeling and design of mistake code examination instrument based on FPGA |
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| Zheng Wenbin,Huang zhixiong,Sun Xiaoting.Modeling and design of mistake code examination instrument based on FPGA[J].CHINA SCIENCE AND TECHNOLOGY INFORMATION,2007(18):107-108. | |
| Authors: | Zheng Wenbin Huang zhixiong Sun Xiaoting |
| Institution: | 1.College of Intormation Science and Engineering, Central South University, Changsha Hunan 410083, China;2.Fujian University of Technology, Fuzhou Fujian 350014, China |
| Abstract: | The paper put forward a project of mistake code examination based on FPGA,and carried out its function on FPGA.That project not only put forward a method of withdrawing a synchronous signal by Phase Lock Loop,but also bring into the thought of"synchronous protection". |
| Keywords: | FPGA PLL Synchronous protection |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ | |