Performance evaluation in image processing with GAPP array processor

The application of parallelism considering the field of image processing is an alternative to implement real time image processing. The data parallelism found in array processors simplify the mapping of this kind of problem as each processing element works on part of the image. The GAPP board (Geometric Arithmetic Parallel Processor) is a near-neighbor mesh architecture with 144 processors interconnected as a 12 × 12 bidimensional array. This work analyzes the performance of the GAPP board regarding image processing. The implementation of two image convolution algorithms and the analyses of the obtained results, as well as the utilization of the GAPP board in this kind of application and the performance achieved are discussed. The results found in this work are also compared to the results presented in [11]. Some ways to achieve a better performance of the GAPP array in this kind of application are also presented.     

A dual interface to Cambridge ring and Ethernet-type local networks

In the Computer Science Department at Strathclyde University an Ethernet-type local network (called Strathnet) and a Cambridge Ring are being installed in parallel, to allow comparisons and experiments on the dual network. The Cambridge Ring is a ‘Polynet’ supplied by Logica VTS Ltd.; in this system the interfaces to our PDP-11s are UMC-Z80 based boards, operating in DMA mode, each UMC board equipped with two parts. The first port is interfaced to a Ring node, using standard Polynet hardware, whereas the second is connected to Strathnet by means of an interface board which we have designed and built to implement a simple subset of the Polynet node register set. This configuration gives an ideal dual access to the two local networks from the PDP-11 hosts in the Department, and avoids the expense of building DMA interfaces to the PDP-11 UNIBUS for Strathnet. Our paper describes the design and implementation of the hardware and software involved in the Strathnet to UMC-Z80 interface, and outlines the way in which the dual system will be used for initial experiments.     

Design of a binary coded decimal integer arithmetic unit

With the increased availability of microprocessors and microcomputers the design engineer has at his disposal the components necessary to design data analysis and control systems at a substantial cost savings over larger computer systems. In many cases, the choice between a computer, minicomputer and microcomputer is based on the speed at which arithmetic functions can be performed. In systems where Binary Coded Decimal (BCD) is a convenient form of data handling, the added overhead of BCD to binary and binary to BCD conversions decreases system performance.This paper describes a hardware BCD addition, subtraction, multiplication and division unit, which performs addition, subtraction and multiplication at speeds greater than the instruction cycle time of most mini and microcomputers (<1 μs, for a 4 digit × 4 digit operation.) and division in less than 10μs. The paper describes the algorithms and hardware utilized in the implementation of the arithmetic unit and discusses interface mechanisms for connecting the unit to a microcomputer.     

An ASIC design for edge detection in real time

An ASIC design for image processing which can implement edge, line and point detection on a single VLSI chip in real time is reported here. The design is based on a set of orthogonal Chebyshev polynomial based operators and consists of a pipelined array of registers and adders with a simple and modular structure which is easily amenable to VLSI implementation. The design has been implemented using VTI design tools on a SUN workstation and the estimated overall chip size is 10.18 mm × 6.92 mm for 1.5 μm CMOS process utilizing about 84,000 transistors. Although the hardware requirements are relatively low, real time processing of a 512 × 512 pixel image can be realized at a clock rate of 8 MHz.     

Parallel picture processing using micro-programmable bit-slice microprocessors

By examining the most frequently encountered picture operations an attempt is made to show that image processing is highly suited to parallel computer architectures. An autonomous image processing system is introduced which comprises three different types of processors and is capable of parallel operations. Attention is specially focused on the architecture and synchronization problems of the microprogrammed bipolar microprocessor modules of the system. Finally the microprogram development aids are briefly discussed and an application example is presented.     

A parallel computer based on simple DSP modules

This article reports on an engineering project at the TUHH aimed at providing a massively parallel experimental computer system to support a number of research projects. The computer nicknamed the PENTAGON is an MIMD system containing a number of identical processing elements (PE's) linked via interfaces. The network is a 3-D torus, and the nodes are based on off-the-shelf signal processor chips, namely TMS 320C40's from TI. The design adds to these standard ingredients an engineering discipline to keep things as simple as possible, and a corresponding, quite unusual physical setup of the total system. These make up for a very cost effective system showing how simple it may be to build a powerful parallel machine.Although based on a standard architecture, the PENTAGON design takes some special choices, the most important being the complete distribution of I/O capabilities. This provides for an unlimited I/O bandwidth, the support of realtime applications and excellent capabilities of expansion. A graphics interface has been designed to provide direct realtime output from the DSP's. Another recent extension is a set of Power-PC modules on top of the DSP nodes.Besides standard commercial compilers for 'C40 networks, the functional language Fifth of the author has been implemented on the PENTAGON. Fifth provides facilities such as distributed objects and the automatical distribution of parallel programs. For well parallelizable applications such as the calculation of a Mandelbrot set, high efficiencies in the usage of the processors have been obtained.     

Function distribution in a list-directed architecture

Over the last few years, there has been a growing interest in function distribution as part of computer architecture. It has been realized that orders of magnitude of execution speed are obtained by redefining the hierarchical levels in computer systems whereas separate optimizing of hardware and software functions procures few percent of enhancement. Direct-Executions Architecture was one of the first attempts to break the ‘natural’ boundary between software and hardware: the elimination of conventional order-codes in favour of higher-order software functions is a good example of vertical migration.We work on a particular direct-execution scheme based on an internal representation of source-programs, derived from LISP. This scheme is founded on the separation of emulation functions into two classes: the formal processing and the effective processing. Our intend is to illustrate how they are supported at each level of the scheme: microprogramming, hardware implementation, system softwares. Finally it is suggested that this partition can offer a good approach to distributed architectures.     

Architecture and C++-programming environment of a highly parallel image signal processor

A highly parallel single-chip image signal processor architecture has been derived by analysis of image processing algorithms. Available levels of parallelism and their associated demands on data access, control and complexity of operations were taken into account. The RISC-architecture, called “HiPAR-DSP”, consists of a control unit, 16 parallel ASIMD-controlled datapaths with autonomous addressing and instruction selection capability, a local data cache per data path, a shared memory with matrix type data access and a powerful DMA-unit. The proposed architecture was designed by assessing the results of an analysis of characteristic algorithm properties with respect to their inherent parallelization resources, achievable speed up and implementation costs. This resulted in a proper balance between the degree of parallelism and flexibility, leading to a high performance for a wide field of applications. Additional measures were taken to support an efficient high level programmability of the processor. This was achieved by the concurrent implementation of special architectural features and a C++-programming environment. It consists of an adaptation of the GNU C++-compiler and an optimizing assembler, supporting all levels of concurrence offered by the hardware. While most levels of parallelization are kept invisible to the programmer, data-level parallelism is expressed by the programmer using special new data types added to the standard C/C++-data-types. A sustained performance of about 2.0 Gigaoperations per second is achieved by the 100 MHz clocked processor for numerous image processing algorithms, leading to a processing time e.g. for a normalized correlation of a 512 × 512 image with a 32 × 32 correlation mask of 450 ms. Thus, a performance is achieved with a programmable parallel processor architecture that hitherto required the application of a dedicated integrated circuit.     

Bus and memory interference in double bus multiprocessor systems

Exact and approximate markovian models are developed for the performance analysis of four multiprocessor architectures based on the availability of two global busses for the interconnection of processors and shared resources such as common memories, I/O devices, etc. The performance index used in the paper is the average number of active processors, called processing power. Exact models show a combinatorial growth of the number of states of the Markov process, whereas the number of states of the approximate models grows linearly with the number of processors in the system. The accuracy of the results yielded by the approximate models is discussed, comparing the processing power estimates with exact results and with simulation. The uniform view used in the development of the models allows a comparison of the efficiency of the four architectures for a given load.     

Hardware programming using C++

The use of a programming language for describing hardware is proposed in this paper. The presented approach, based on minor extensions of C++, gives an attractive way to program computers with reconfigurable hardware elements (i.e. FPGAs). It can also be used as a common implementation-level language for hardware-software codesign frameworks.The proposed approach differs from other codesign methodologies due to the use of a single, object oriented, notation for all design levels; from the most abstract OMT notations, where the system's functionality and requirements are first captured, to the detailed implementation-level C++ code.     

The SUMA microprogramming system

SUMA (Simple but Useful Microprogramming Aid) is a machine independent higher level language programming system designed to aid the microprogrammer in the production of structured microcode algorithms for horizontal micro-architectures. Unlike other systems SUMA can be used to produce efficient microcode for a wide range of microprogrammable machine architectures without the need to produce a new tailored translater for each target machine.     

HLL enhancement for stack based processors

Stack machines, or stack based processors, have long been pigeon-holed as FORTH processors; specialised devices with little relevance for high level language applications. The failure of stack machines to address the issue of high level language support, and C in particular, has prevented wider acceptance of this promising technology despite the potential benefits of simpler hardware and low gate counts. Our research has centred upon eliminating cache and memory dependence, reducing the limits imposed by external bandwidths^◊. Having previously introduced a compact multiple-instruction-per-word stack-based encoding strategy in [Bailey93a], we now present a revised model, assessing its performance with compiled C benchmarks^⧫, and stressing minimisation of memory dependence.     

图书馆整体形象设计研究

图书馆整体形象的营造与维护是对现代图书馆管理职能的强化,是图书馆日常工作的重要内容之一。人的感官系统所相关的视觉、听觉、触觉的形象设计与图书馆各项工作息息相关,好的设计给人们带来一种温馨、自然和舒适的感觉。图书馆是资讯流通的场所,图书馆办公用品、图书馆学报、橱窗宣传栏、礼貌语言以及背景音乐等设计看似简单,但要有一个新的创意的确不容易。本文分析与研究目前图书馆整体形象设计中的某些实务问题,并介绍了国内外优秀的成功设计经验。     

On the optimal mapping of fuzzy rules on standard micro-controllers

Once a fuzzy controller is specified by a rule-set, it can be implemented in dedicated hardware or as a software program. For industrial applications, an inexpensive micro-controller with limited resources is often selected. The implementation (or mapping) issue then leads to a tradeoff between operation speed and memory usage. This paper presents a set of basic transformation rules that allows the designer to optimize such a mapping.     

A C-MOVE architecture based multiprocessor system for encoding Walsh-Hadamard transformed images

A novel architecture has been proposed based on the C-MOVE microprocessor for the fast and efficient parallel structural decomposition, W-H transform and encoding of digital images. A hierarchical and reconfigurable tree of interconnected processors is used to implement the W-H transform of an image which is already preprocessed and decomposed into a succession of consecutive “quadrant” sub-pictures.The regular decomposition procedure is followed to develop the quad-tree structure associated with a given image. Then a parallel algorithm is developed for the realization of the W-H transform of the given image. The W-H transform of the whole picture can be implemented by parallel processing.The C-MOVE architecture has been invoked for the realization of the above mentioned scheme. The C-MOVE architecture can prove to be extremely economical and fast, especially when a large number of parallel processors is utilized.The tree-structure of the decomposed picture and the proposed hierarchically distributed processing scheme match very well, resulting in a very flexible and adaptable architecture for implementing an image processing scheme.The proposed scheme uses C-MOVE processors to implement all the modules of the system.The architecture presented exhibits a high degree of parallelism with the main processing modules sharing the same main memory and exchanging data over the common very high speed bus, under the control of the master-controller processor. Each module works independently on the assigned task once the data and instruction string have been loaded in its part of memory. Meanwhile, the picture preprocessing module is freed to proceed on the next step of the regular decomposition algorithm.     

屏幕保护程序在图书馆信息推送服务中的应用

每台计算机均可在屏幕保护状态下运行设定的图像与文字,图书馆为读者配备的公用计算机越来越多,处于大庭广众视野中的这些公用计算机为图书馆进行信息推送服务提供了硬件平台.文章通过成功案例分析了充分利用屏保程序这样一个看似闲置的功能来实现图书馆信息推送服务的应用前景,阐述了图书馆可寻求的细微创新服务举措.     

Software support in hardware

Until the recent past, hardware designers paid little attention to software needs in the more global area of system requirements. They concentrated their efforts more on computational improvements. The hardware-software interface remained largely untouched.This situation has changed almost dramatically in the last few years. Upcoming hardware tends to exploit the capabilities of microelectronics, i.e., VLSI technology, in order to provide additional software support. The most visible approach so far has been a redistribution of functions: peripheral and memory controllers assume a multitude of administrative tasks; attached processors handle specific computational tasks. But right now, real software primitives are also being forged into hardware: operating system support as well as high-level language interpretation are prime candidates in this area. Using actual examples, an account of such efforts is being presented.     

Design of a kernel for implementing communication protocols

We describe the design of a kernel for an inexpensive front-end processor to run the lower layers of common communication protocols. Implementing a full fledged kernel on a card requires large memory, expensive hardware and heavy processing overhead. We studied the requirements of the layers of communication protocols which generally run as a part of the host kernel. We realised that a workable kernel for the front-end processor which has a subset of the features of the host kernel, could be implemented within reasonable time. This could provide the functions required by the communication protocol layers and run them within the constraints of inexpensive hardware. The aims of this research were manifold:

• 1.(1) To explore the general set of requirements of common connection-oriented and connectionless protocols.
• 2.(2) To design and present algorithms of a kernel which can satisfy such requirements. Since the kernel is based on this general set of requirements, it will be generic and not specific to only the protocol running on the card. Thus it can be used to download different protocols on the card.
• 3.(3) Suggest implementation techniques so as to reduce memory and processing overhead on the host and to improve the performance of the protocols running in the kernel.
• 4.(4) To actually run a protocol on this kernel and compare its performance with an existing design.

     

关于信息管理与信息系统专业若干问题的思考

信息管理与信息系统专业是培养具备管理信息系统分析与设计和对系统内信息资源的开发与利用能力的人才。课程设置中 ,管理学、经济学及其分支课程是建立管理信息系统所需知识 ;信息管理学及其分支课程是建立管理信息系统内信息资源开发与利用所需知识。由管理学、经济学、计算机科学和信息管理学等 4门学科知识构成了其全新的边缘性和综合性专业定位。参考文献 9。     

Telinet网点对点信息传递系统的开发

点对点信息传递是目前计算机局域网络应用中的重要研究内容。笔者在自行设计的Ｔｅｌｉｎｅｔ（Ｔｅｌｅｐｈｏｎｅｌｉｎｅｎｅｔｏｗｒｋ）局域网上成功地开发出了一个实现点对点信息传递的实际系统。本文论述了该系统的开发环境、系统组成、具备的功能和具体实现（包括协议设计），最后简单地介绍了实现过程中的一些关键技术