High-performance hardware architecture of elliptic curve cryptography processor over GF(2163)

We propose a novel high-performance hardware architecture of processor for elliptic curve scalar multiplication based on the Lopez-Dahab algorithm over GF(2163) in polynomial basis representation. The processor can do all the operations using an efficient modular arithmetic logic unit, which includes an addition unit, a square and a carefully designed multiplication unit. In the proposed architecture, multiplication, addition, and square can be performed in parallel by the decomposition of computation. The point addition and point doubling iteration operations can be performed in six multiplications by optimization and solution of data dependency. The implementation results based on Xilinx Virtexll XC2V6000 FPGA show that the proposed design can do random elliptic curve scalar multiplication GF(2163) in 34.11 μs, occupying 2821 registers and 13 376 LUTs.     

Highly parallel implementation of sub-pixel interpolation for AVS HDTV decoder

In this paper, we propose an effective VLS1 architecture of sub-pixel interpolation for motion compensation in the AVS HDTV decoder. To utilize the similar arithmetical operations of 15 luma sub-pixel positions, three types of interpolation filters are proposed. A simplified multiplier is presented due to the limited range of input in the chroma interpolation process. To improve the processing throughput, a parallel and pipelined computing architecture is adopted. The simulation results show that the proposed hardware implementation can satisfy the real-time constraint for the AVS HDTV （1 920× 1 088） 30 fps decoder by operating at 108 MHz with 38.18k logic gates. Meanwhile, it costs only 216 cycles to accomplish one macroblock, which means the B frame sub-pixel interpolation can be realized by using only one set of the proposed architecture under real-time constraints.     

基于流水线结构的可重构AES算法IP核的硬件实现(英文)

为了提高AES算法中IP核数据的吞吐量并同时减小硬件资源的占用,以达到速度和面积的折中实现,采用混合流水线结构和可重构技术完成了IP核的设计.该设计包括在同一个混合流水线结构的流程中实现了AES算法的加密和解密过程;根据有限域的性质,对AES算法中的Sbox盒进行了优化;结合可重构技术,完成了对AES轮变换的主要构件ShiftRow和MixColumn的优化.本设计在Xilinx Virtex2p xc2vp20-7 FPGA器件上完成,其数据吞吐量达到2.58Gbit/s,所需组合逻辑仅为3 233块,通过与同型号器件上的其他设计进行对比,实现了速度和面积的折中,在吞吐量和面积上都得到了比较理想的结果.     

High-performance hardware architecture of elliptic curve cryptography processor over GF（2^163）

We propose a novel high-performance hardware architecture of processor for elliptic curve scalar multiplication based on the Lopez-Dahab algorithm over GF（2^163） in polynomial basis representation. The processor can do all the operations using an efficient modular arithmetic logic unit, which includes an addition unit, a square and a carefully designed multiplication unit. In the proposed architecture, multiplication, addition, and square can be performed in parallel by the decomposition of computation. The point addition and point doubling iteration operations can be performed in six multiplications by optimization and solution of data dependency. The implementation results based on Xilinx VirtexⅡ XC2V6000 FPGA show that the proposed design can do random elliptic curve scalar multiplication GF（2^163） in 34.11 μs, occupying 2821 registers and 13 376 LUTs.     

一种适用于NAND闪存的LDPC译码算法

由于NAND闪存具有读写速度快、效率高、功耗低等特点,因此被广泛应用于存储领域。为了提高闪存存储的可靠性,提出一种适用于NAND闪存的LDPC译码算法对其进行纠错。基于LDPC码的BP译码简化算法,结合分层算法与归一化最小和（NMS）算法,提出一种改进的行分层最小和算法。仿真结果表明,改进译码算法在不降低译码性能的前提下,减少了迭代次数,加快了译码收敛速度,更有利于硬件电路的实现。     

将C算法转换为Verilog HDL实现的一种改进方法

本文在分析软件算法和硬件实现的不同特点的基础上,结合C语言算法和HDL硬件实现的特点,提出了将C算法转换为HDL实现的一种改进方法。通过求最大公因数的例子,说明了改进前后的方法在资源利用和最大工作频率方面的差距并不是很明显,但改进后的方法比改进前的方法简洁实用,易于理解和操作。本文提出的改进方法优势明显,具有更广泛的应用前景,对于一般C语言算法的硬件实现具有适用性和指导意义。     

浅谈RSA密码算法及应用

RSA算法能同时用于加密和数字签名,并能实现密钥分发功能,也易于理解和操作.它的安全性依赖于大数分解,但是否等同大数分解,还没有理论上的证明.RSA算法普遍被认为是目前最优秀的,使用最广泛的非对称密码体制,它经历了20多年的攻击考验,才被人们接受.     

RSA加密算法在网络监听中的应用

信息在网络传输过程中存在被监听的安全隐患,保护信息免受监听技术威胁的常见方法是对信息进行加密,目前最理想的加密算法是RSA算法。文章论述了网络监听原理,检测方法及其防范措施,对RSA算法进行详细地描述并编程实现。通过理论和实验结果分析,RSA算法保证了信息的保密性和完整性,能有效防止信息被监听。     

基于混沌映射、小波变换和RSA加密的数字水印算法

本文提出了一种新的公开算法的数字水印算法。该算法首先应用Logistic映射构造了一个原始图像的子图,其次把DWT变换作用在这个子图上得到两个子带LH1和HL1,然后对这两个子带进行RSA加密并把水印嵌入在这两个被加密的子带上,接着解密这两个子带并通过IDWT变换重构子图,最后按构成子图的顺序把每一个8×8像素的小块放回到原图中相应位置,从而得到了一个嵌入了水印信息的图像。实验结果表明,通过该算法嵌入的水印具有较好的鲁棒性、安全性和不可感知性。     

对RSA密码系统旁路攻击的防御

Based on the structure of the side channel attacks (SCAs) to RSA cryptosystem can resist the fault attack andcombine with the randomization method for the message and secret exponent, a new implementation scheme of CRT-based(the Chinese remained theorem) RSA is proposed. The proposed scheme can prevent simple power analysis (SPA), differentialpower analysis (DPA) and time attack, and is compatible with the existing RSA-CRT cryptosystem as well. In addition, animprovement for resisting fault attack is proposed, which can reduce extra computation time.     

Architecture Singularity Analysis of 4-U■S/U■U 5-DOF Parallel Mechanism

Architecture singularity of a parallel mechanism with five degrees of freedom (DOF) is analyzed. Such mechanism consists of a movable platform connected to the base by five active limbs. Four of them are identical 6-DOF limbs and the last one has the same DOF as the specified DOF of the movable platform. Based on the kinematics analysis, two categories of architecture singularities for such mechanism are proposed. Then the sufficient condition for each singularity is researched. Results show that the mechanism is singular when it employs each category of the proposed architecture, provided that it satisfies the corresponding sufficient condition. It can be concluded that the proposed two categories of architecture singularities should be avoided with the following dimensional synthesis of such mechanism.     

Architecture Singularity Analysis of 4-U PS/U PU 5-DOF Parallel Mechanism

Architecture singularity of a parallel mechanism with five degrees of freedom (DOF) is analyzed. Such mechanism consists of a movable platform connected to the base by five active limbs. Four of them are identical 6-DOF limbs and the last one has the same DOF as the specified DOF of the movable platform. Based on the kinematics analysis, two categories of architecture singularities for such mechanism are proposed. Then the sufficient condition for each singularity is researched. Results show that the mechanism is singular when it employs each category of the proposed architecture, provided that it satisfies the corresponding sufficient condition. It can be concluded that the proposed two categories of architecture singularities should be avoided with the following dimension-al synthesis of such mechanism.     

Forward displacement analysis of a redundant parallel manipulator by approximation algorithms

This paper presents the forward displacement analysis of an 8-PSS （prismatic-spherical-spherical） redundant parallel manipulator whose moving platform is linked to the base platform by eight kinemtic chains consisting of a PSS joint and a strut with fixed length. A general approximation algorithm is used to solve the problem. To avoid the extraction of root in the approximation process, the forward displacement analysis of the 8-PSS redundant parallel manipulator is transformed into another equivalent problem on the assumption that the strut is extensible while the slider is fixed. The problem is solved by a modified approximation algorithm which predicates that the manipulator will move along a pose vector to reduce the difference between the desired configuration and an instantaneous one, and the best movement should be with minimum norm and least quadratic sum. The characteristic of this modified algorithm is that its convergence domain is larger than that of the general approximation algorithm. Simulation results show that the modelified algorithm is general and can be used for the forward displacement analysis of the redundant parallel manipulator actuated by a revolute joint.     

RSA算法的安全参数研究

RSA算法是最著名和可靠的非对称密钥加密算法。本文系统地介绍了RSA公钥密码算法的基本原理及利用RSA算法进行数据加密的过程;对RSA公钥密码算法安全参数的选择进行分析,并探讨了安全参数的选择对RSA公钥密码算法的安全性影响及重要性。     

RSA加密中大素数的生成方法及其改进

RSA加密算法的安全性是基于两个大素数的乘积用目前的计算机水平无法分解这一前提,生成两个满足长度要求的大素数,能够保证RSA加密数据的安全可靠。文章在对RSA算法基本原理及加、解密过程进行介绍的基础上,比较了几种常见检测素数的方法,并对个别算法进行了改进。综合它们的优缺点提出了一种新的生成安全大素数的方法及计算机实现相应算法的步骤。     

RS(255,239)解码器并行钱氏搜索电路的面积优化

提出了一个全局优化算法(GOA)对RS(255,239)解码器中的并行钱氏搜索电路进行面积优化.通过查找钱氏搜索电路中GF (Galois field)常数乘法器的公共模2加运算并进行预运算,GOA能够有效地减少电路中异或门的数量,从而减少电路面积.与原有局部优化方法不同,GOA是一个全局优化算法.当每次迭代中同时有多个最大匹配对时,GOA通过选取与其他匹配对关系最小的一对作为最优匹配而不是随机地选择一对,使得当前结果对最终的优化结果影响最小.进一步将基于组的GOA用于GF乘法器组的优化,结果显示相对于直接实现方法,可使并行钱氏搜索电路的面积减少51%,而对GF乘法器的单独优化也能使电路面积减少26%.该优化方法可广泛地用于含有大量模2加运算的并行结构中.     

Gradual refinement for application-specific MPSoC design from Simulink model to RTL implementation

The application-specific multiprocessor system-on-chip （MPSoC） architecture is becoming an attractive solution to deal with increasingly complex embedded applications, which require both high performance and flexible programmability. As an effective method for MPSoC development, we present a gradual refinement flow starting from a high-level Simulink model to a synthesizable and executable hardware and software specification. The proposed methodology consists of five different abstract levels： Simulink combined algorithm and architecture model （CAAM）, virtual architecture （VA）, transactional accurate architecture （TA）, virtual prototype （VP） and field-programmable gate array （FPGA） emulation. Experimental results of Motion-JPEG and H.264 show that the proposed gradual refinement flow can generate various MPSoC architectures from an original Simulink model, allowing processor, communication and tasks design space exploration.     

Parallel programming characteristics of a DSP-based parallel system

INTRODUCTION DSP-based parallel system is a kind of high- performance parallel computer which uses parallel accelerating boards based on SHARC DSP chip (Kuo and Gan, 2005) as plug-in boards and inserts them into the military reinforcing computer, military fault-tolerant computer, even the personal computer. The parallel accelerating board based on SHARC DSP is a high-performance parallel processing board-level product developed by the Wuhan Digital Engineering Institute and is su…     

Cell BE高性能计算实验平台设计与实现

Cell BE为一个异构多核并行处理架构,具有超高速通信能力,能够有效地提供超级计算机的性能。在分析与研究Cell BE的硬件架构、并行编程环境与模型的基础上,选取PS3为主机,构建一个CellBE高性能计算实验平台。通过选取相关的硬件设备,在构建好硬件平台的基础上,构建系统与软件平台。通过在实验平台上运行高性能计算应用程序,来对平台进行实验测试。以求解多体问题的计算为平台实验应用程序,将四叉树计算初始化过程算法在Cell BE实验平台上实现,并进行运行测试。在不同的粒子数实验规模下的计算时间结果表明,在Cell BE平台上获得了较高的对CPU的加速效果。     

Depth estimation system suitable for hardware design

Depth estimation is an active research area with the developing of stereo vision in recent years. It is one of the key technologies to resolve the large data of stereo vision communication. Now depth estimation still has some problems, such as occlusion, fuzzy edge, real-time processing, etc. Many algorithms have been proposed base on software, however the performance of the computer configurations limits the software processing speed. The other resolution is hardware design and the great developments of the digital signal processor (DSP), and application specific integrated circuit (ASIC) and field programmable gate array (FPGA) provide the opportunity of flexible applications. In this work, by analyzing the procedures of depth estimation, the proper algorithms which can be used in hardware design to execute real-time depth estimation are proposed. The different methods of calibration, matching and post-processing are analyzed based on the hardware design requirements. At last some tests for the algorithm have been analyzed. The results show that the algorithms proposed for hardware design can provide credited depth map for further view synthesis and are suitable for hardware design.