Highly parallel implementation of sub-pixel interpolation for AVS HDTV decoder

In this paper, we propose an effective VLS1 architecture of sub-pixel interpolation for motion compensation in the AVS HDTV decoder. To utilize the similar arithmetical operations of 15 luma sub-pixel positions, three types of interpolation filters are proposed. A simplified multiplier is presented due to the limited range of input in the chroma interpolation process. To improve the processing throughput, a parallel and pipelined computing architecture is adopted. The simulation results show that the proposed hardware implementation can satisfy the real-time constraint for the AVS HDTV （1 920× 1 088） 30 fps decoder by operating at 108 MHz with 38.18k logic gates. Meanwhile, it costs only 216 cycles to accomplish one macroblock, which means the B frame sub-pixel interpolation can be realized by using only one set of the proposed architecture under real-time constraints.     

Analysis and application of error concealment tools in AVS-M decoder

Audio Video coding Standard (AVS) is the latest audio and video coding standard of China. AVS Part 7 (also known as A VS-M) targets mobility applications where error concealment is of great importance. This paper first briefly introduces the general concept of error concealment. Then two error concealment schemes are proposed and implemented on AVS-M decoder under different test conditions. Simulation results of the schemes and suggestions on how to use these tools are also provided.