High throughput bandwidth optimized VLSI design for motion compensation in AVS HDTV decoder

In this paper we present a motion compensation （MC） design for the newest Audio Video coding Standard （AVS） of China. Because of compression-efficient techniques of variable block size （VBS） and sub-pixel interpolation, intensive pixel calculation and huge memory access are required. We propose a parallel serial filtering mixed luma interpolation data flow and a three-stage multiplication free chroma interpolation scheme. Compared to the conventional designs, the integrated architecture supports about 2.7 times filtering throughput. The proposed MC design utilizes Vertical Z processing order for reference data re-use and saves up to 30% memory bandwidth. The whole design requires 44.3k gates when synthesized at 108 MHz clock frequency using 0.18-μm CMOS technology and can support up to 1920×1088@30 fps AVS HDTV video decoding.     

Parallel processing architecture of H.264 adaptive deblocking filters

In H.264, computational complexity and memory access of deblocking filters are variable, dependent on video contents. This paper proposes a VLSI architecture of deblocking filters with adaptive dynamic power, which avoids redundant computations and memory accesses by precluding the blocks that can be skipped. The vertical and horizontal edges are simultaneously processed in an advanced scan order to speed up the decoder. As a result, dynamic power of the proposed architecture can be reduced adaptively （up to about 89%） for different videos, and the off-chip memory access is improved when compared to previous designs. Moreover, the processing capability of the proposed architecture is in particular appropriate for real-time deblocking of high-definition television （HDTV, 1920× 1080 pixels/frame, 60 frames/s video signals） video operation at 62 MHz. Using the proposed architecture, power can be reduced by up to about 89% and processing time by from 25% to 81% compared with previous designs.     

Analysis and application of error concealment tools in AVS-M decoder

Audio Video coding Standard (AVS) is the latest audio and video coding standard of China. AVS Part 7 (also known as A VS-M) targets mobility applications where error concealment is of great importance. This paper first briefly introduces the general concept of error concealment. Then two error concealment schemes are proposed and implemented on AVS-M decoder under different test conditions. Simulation results of the schemes and suggestions on how to use these tools are also provided.     

Analysis and application of error concealment tools in AVS-M decoder

Audio Video coding Standard (AVS) is the latest audio and video coding standard of China. AVS Part 7 (also known as AVS-M) targets mobility applications where error concealment is of great importance. This paper first briefly introduces the general concept of error concealment. Then two error concealment schemes are proposed and implemented on AVS-M decoder under different test conditions. Simulation results of the schemes and suggestions on how to use these tools are also provided.     

面向AVS标准的数字电视中间件的研究

AVS是具有自主知识产权的先进的视音频编解码标准,包含系统-广播、视音频编码及IP网络环境等九大部分。中间件是实现数字电视交互业务不可或缺的软件平台,针对AVS标准,中间件主要涉及其第一和第八部分。因此,建立面向AVS标准的中间件体系结构,是一件有意义的也是非常必要的工作,本文对此作了较为深入的研究与探讨。     

一种有效的golomb解码器设计与硬件实现

Golomb编码压缩算法已被广泛地应用于视频图像处理、测试数据压缩等众多领域。本文设计了一种有效的适合硬件实现的Golomb解码器,并且完成了解码器电路的硬件实现。本设计采用有限状态机(FSM)与计数器相结合的解码结构,并且对有限状态机的实现进行了优化,减少了有限状态机的状态数。电路综合实验结果表明,此解码器的电路门数大约为120门,关键路径延时为0.7ns。该设计可扩展性强、硬件开销少,可在较高的工作频率下工作,并且可以作为独立的IP核使用。     

Fast Sub-Pixel Motion Estimation Algorithm For H.264

The latest international coding standard H.264/AVC[1]extends motion compensation to quarter-sampleaccuracy[2]. Generally,integer-pixel motion search costsmuch more time than sub-pixel search during which 16points are checked in total when implemented in f…     

基于Canny和双线性插值的镍片边缘提取算法

手机锂电池保护板在生产过程中需要利用视觉检测镍片角度偏差、折叠等各类缺陷,但由于镍片尺寸小且这些缺陷在灯光下会产生不同程度的反光,导致获得的镍片图像边缘不清晰。为此,本研究提出了一种基于Canny算子和双线性插值的高亮镍片边缘提取算法。首先对原始图像分割出感兴趣区域并进行灰度处理,再利用Canny算子提取其像素级边缘,最后用双线性插值法提取其亚像素级边缘。为验证该算法的有效性,将其与工程中常用的Sobel 边缘提取算法进行实验对比,计算边缘内部包含面积的像素数量、等级及边缘提取的时间,判断两类算法在精度和效率上的优劣。实验结果表明,基于Canny 算子和双线性插值的高亮镍片边缘提取算法能精准提取镍片的亚像素边缘,提取的像素精度达到了0.1 pixel,平均边缘提取时间为0.835 s,比Sobel 节省了20.57%的时间,能够满足工业生产的精度需求与效率要求。     

RS(255,239)解码器并行钱氏搜索电路的面积优化

提出了一个全局优化算法(GOA)对RS(255,239)解码器中的并行钱氏搜索电路进行面积优化.通过查找钱氏搜索电路中GF (Galois field)常数乘法器的公共模2加运算并进行预运算,GOA能够有效地减少电路中异或门的数量,从而减少电路面积.与原有局部优化方法不同,GOA是一个全局优化算法.当每次迭代中同时有多个最大匹配对时,GOA通过选取与其他匹配对关系最小的一对作为最优匹配而不是随机地选择一对,使得当前结果对最终的优化结果影响最小.进一步将基于组的GOA用于GF乘法器组的优化,结果显示相对于直接实现方法,可使并行钱氏搜索电路的面积减少51%,而对GF乘法器的单独优化也能使电路面积减少26%.该优化方法可广泛地用于含有大量模2加运算的并行结构中.     

MPEG-2纹理图像的错误检测技术

基于MPEG-2码流，描述了传送流（TS）和视频流的错误检测方法。这两种错误分别由信道解码器和视频解码器识别，通常检测到的是语法错误，而且由于可变字长码的错误传播影响，检测到的错误位置并非错误的起始位置。因此，基于图像光滑性和一致性的假设，提出了非语法错误的纹理图像的检测算法（如DC系数的错误检测算法）以及确定错误起始位置的方法。实验结果表明，该技术能够应用于MPEG-2解码器的实时处理。     

Efficient video downscaling transcoder from MPEG-2 to H.264

The new H.264 video coding standard achieves significantly higher compression performance than MPEG-2. As the MPEG-2 is popular in digital TV, DVD, etc., bandwidth or memory space can be saved by transcoding those streams into H.264 in these applications. Unfortunately, the huge complexity keeps transcoding from being widely used in practical applications. This paper proposes an efficient transcoding architecture with a smart downscaling decoder and a fast mode decision algorithm. Using the proposed architecture, huge buffering memory space is saved and the transcoding complexity is reduced. Performance of the proposed fast mode decision algorithm is validated by experiments.     

Fault-tolerant design of spaceborne mass memory system

A fault-tolerant spaceborne mass memory architecture is presented based on entirely commercial-off-theshelf components.The highly modularized and scalable memory kernel supports the hierarchical design and is well suited to redundancy structure.Error correcting code(ECC) and periodical scrubbing are used to deal with bit errors induced by single event upset.For 8-bit wide devices, the parallel Reed Solomon(10, 8) can perform coder/decoder calculations in one clock cycle, achieving a data rate of several Gb/...     

Efficient VLSI architecture of CAVLC decoder with power optimized

This paper presents an efficient VLSI architecture of the contest-based adaptive variable length code (CAVLC) decoder with power optimized for the H.264/advanced video coding (AVC) standard. In the proposed design, according to the regularity of the codewords, the first one detector is used to solve the low efficiency and high power dissipation problem within the traditional method of table-searching. Considering the relevance of the data used in the process of runbefore’s decoding, arithmetic operation is combined with finite state machine (FSM), which achieves higher decoding efficiency. According to the CAVLC decoding flow, clock gating is employed in the module level and the register level respectively, which reduces 43% of the overall dynamic power dissipation. The proposed design can decode every syntax element in one clock cycle. When the proposed design is synthesized at the clock constraint of 100 MHz, the synthesis result shows that the design costs 11 300 gates under a 0.25 μm CMOS technology, which meets the demand of real time decoding in the H.264/AVC standard.     

一种测量钛酸钡/聚氨酯材料电致伸缩性能的新方法

提出利用数字散斑相关方法测量材料的电致伸缩性能的新方法.通过数字散斑相关方法得到面内位移,从而由几何三角关系得到离面位移,实现电致伸缩应变的测量.采用该方法对高电场作用下钛酸钡/聚氨酯复合高分子材料的电致伸缩性能进行了测量.在高电场作用下,对重复加电放电过程进行分析,得到电致伸缩应变,从而获取材料的电致伸缩系数.实验中采用双线性插值方法获取亚象素灰度值,以提高测量精度,并将结果与曲面拟合算法的计算结果进行了比较.结果表明:钛酸钡的加入提高了聚氨酯材料的电致伸缩性能;数字散斑相关方法可以有效地实现材料的电致伸缩系数的测量.该方法为电致伸缩性能的研究提供了一种有效的工具.     

A parallel memory architecture for video coding

To efficiently exploit the performance of single instruction multiple data （SIMD） architectures for video coding, a parallel memory architecture with power-of-two memory modules is proposed. It employs two novel skewing schemes to provide conflict-free access to adjacent elements （8-bit and 16-bit data types） or with power-of-two intervals in both horizontal and vertical directions, which were not possible in previous parallel memory architectures. Area consumptions and delay estimations are given respectively with 4, 8 and 16 memory modules. Under a 0.18-pm CMOS technology, the synthesis results show that the proposed system can achieve 230 MHz clock frequency with 16 memory modules at the cost of 19k gates when read and write latencies are 3 and 2 clock cycles, respectively. We implement the proposed parallel memory architecture on a video signal processor （VSP）. The results show that VSP enhanced with the proposed architecture achieves 1.28× speedups for H.264 real-time decoding.     

Combined Signal Detection Method in Differential Frequency Hopping System

Differential frequencyhopping(DFH) as a digital radiotechnology has satisfyingfeatures of multipathfading mitiga-tion,spectral re-use ,non-interferingspreadspectrumoper-ation,andinterferenceresistance[1].Sincetheintroductionof controllable redundancy into…     

基于机器视觉的车道标志线检测研究

针对车辆辅助驾驶或自主驾驶中的车道保持问题, 研究了基于视觉的车道标志线实时检测方法. 介绍了系统组成、工作原理和车道模型, 并着重讨论了车道图像的检测算法. 其主要思想是在图像上选取几个合适的处理区域, 通过对每个处理区域进行适当的预处理、边缘检测和霍夫变换等过程来提取车道描述特征. 试验结果表明, 该方法具有实时性好、识别可靠性高等特点, 在一定程度上能为后续的辅助驾驶或自主驾驶提供决策依据.     

基于两级插补机制的NURBS曲线插补器研究

针对非均匀有理B 样条 (non uniform rational B spline, NURBS)曲线高速高精加工过程中计算负载高的问题,提出一种基于两级插补机制的NURBS曲线插补器方案,在主控端执行第一级插补,完成曲线预处理等粗插补工作;在运动控制端执行第二级插补,完成加减速及实时位置输出等精插补工作。同时,设计并开发基于ARM FPGA架构的实验平台,可用于两级插补器的实验验证,具有一定的现实参考意义。     

苏州河底泥重金属形态分析

Nine elements （As, Cd, Cr, Cu, Fe, Mn, Ni, Pb, Zn） in sediment samples at 7 sites （Site 1-7） from Suzhou Creek in Shanghai were analyzed with the Community Bareau of Reference （BCR） （sequential extraction （SE）） protocol and simultaneously extracted metals （SEM）/acid volatile sulfide （AVS） procedure to assess the metal bioavailability and toxicology in this area. The results showed that the BCR extraction can be utilized as an additional tool with the AVS method for assessing the potential bioavailability and toxicity of metals in sediments. Pollution from S5 （Site 5） was more severe than from other sites, especially Pb, Cu and Zn. Among all the sites, more than 80% of the total concentration of Fe existed in the residual fraction, As, Cr, Mn also dominated in the residual fraction （more than 50%）. While Cd, Ni and Zn （more than 35%） were mainly in the non-stable phase. Cu had a strong affinity with oxidizable phase and Pb varied from site to site. The SEM/AVS ratio was less than one in these sediments and results implied that the majority of Zn and Ni （〉 40%） were bound to AVS. In contrast, Pb, Cu and Cd were little bound to AVS due to their low ration of SEM-Pb, Cu, Cd to corresponding total concentration and relatively high Dorewater concentration.     

信息系统可靠性管理研究

An integrated intelligent management is presented to help organizations manage many heterogeneous resources in their information system. A general architecture of management for information system reliability is proposed, and the architecture from two aspects, process model and hierarchical model, described. Data mining techniques are used in data analysis. A data analysis system applicable to real-time data analysis is developed by improved data mining on the critical processes. The framework of the integrated management for information system reliability based on real-time data mining is illustrated, and the development of integrated and intelligent management of information system discussed.