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The State Transition Equation (STE) based method to automatically generate the parallel CRC circuits for any generator polynomial
or required amount of parallelism is presented. The parallel CRC circuit so generated is partially optimized before being
fed to synthesis tools and works properly in our LAN transceiver. Compared with the cascading method, the proposed method
gives better timing results and significantly reduces the synthesis time, in particular.
Project (No. 60271010) supported by the National Natural Science Foundation of China 相似文献
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INTRODUCTIONCRC (CyclicRedundancyChecking)codesarewidelyusedintelecommunication ,especiallyintheinternallayersofprotocolssuchasEther net,X2 5,FDDIandATM (AAL5) .Thecom monhardwaresolutionforCRCcalculationisthelinearfeedbackshiftregister (LFSR) ,charac ter… 相似文献
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