DNA-Computing – ein funktionales Modell im laborpraktischen Experiment

Zusammenfassung.   Im Zentrum der Betrachtungen zum DNA-Computing steht die Frage nach den Chancen und Grenzen dieses neuen Berechnungsmodells, nachdem in den letzten Jahren eine rasante Entwicklung auf das Thema aufmerksam machte. Neben beachtlichen theoretischen Untersuchungen zum “Rechnen im Reagenzglas” werden auch laborpraktische Implementierungen favorisiert. An der TU Dresden wurde in interdisziplin?rer Arbeit ein Integer-Rucksackproblem mittels eines DNA-Algorithmus im Labor gel?st und dabei eine Vielzahl molekularbiologischer Operationen analysiert. Mit Hilfe dieses Satzes von Operationen gelang eine universelle und labornahe Modellierung des DNA-Computing. Hierbei angewandte Techniken und Methoden werden vorgestellt und bewertet. Die Beschreibung des DNA-Algorithmus zeigt, wie sich Einzeloperationen vorteilhaft zu Operationsfolgen zusammensetzen lassen und gemeinsam mit einer geeigneten DNA-Kodierung der Eingangsdaten zur L?sung des Problems im Labor führen. Erstmalig wurden hierbei natürliche Zahlen verarbeitet. Die Arbeitsgemeinschaft DNA-Computing Dresden konzentriert sich auf Aufgabenstellungen, die formale Modelle des DNA-Computing mit überzeugenden Laborimplementierungen verbinden. Eingegangen am 14. Februar 2000 / Angenommen am 26. Oktober 2000     

A parallel memory architecture for video coding

To efficiently exploit the performance of single instruction multiple data （SIMD） architectures for video coding, a parallel memory architecture with power-of-two memory modules is proposed. It employs two novel skewing schemes to provide conflict-free access to adjacent elements （8-bit and 16-bit data types） or with power-of-two intervals in both horizontal and vertical directions, which were not possible in previous parallel memory architectures. Area consumptions and delay estimations are given respectively with 4, 8 and 16 memory modules. Under a 0.18-pm CMOS technology, the synthesis results show that the proposed system can achieve 230 MHz clock frequency with 16 memory modules at the cost of 19k gates when read and write latencies are 3 and 2 clock cycles, respectively. We implement the proposed parallel memory architecture on a video signal processor （VSP）. The results show that VSP enhanced with the proposed architecture achieves 1.28× speedups for H.264 real-time decoding.     

并行信息检索及其相关技术

本文讨论了并行检索的要点、作用及相关体系结构。重点对MIMD体系结构和SIMD体系结构进行了探讨。     

SM4的快速软件实现技术

SM4是中国分组密码国家标准,广泛应用于各种信息系统和安全产品。某些应用环境对密码算法的软件实现性能有很高的需求。目前SM4的软件实现方法仅限于查表实现,因此,研究SM4算法的快速软件实现技术很重要。利用SIMD技术,给出SM4的软件优化实现。与目前基于查表的软件实现相比,它有明显优势。在Intel Core i7-6700处理器上,相比于查表方法,利用SIMD技术的软件实现性能提高1.38倍。     

A complexity-scalable software-based MPEG-2 video encoder

With the development of general-purpose processors (GPP) and video signal processing algorithms, it is possible to implement a software-based real-time video encoder on GPP, and its low cost and easy upgrade attract developers' interests to transfer video encoding from specialized hardware to more flexible software. In this paper, the encoding structure is set up first to support complexity scalability; then a lot of high performance algorithms are used on the key time-consuming modules in coding process; finally, at programming level, processor characteristics are considered to improve data access efficiency and processing parallelism. Other programming methods such as lookup table are adopted to reduce the computational complexity. Simulation results showed that these ideas could not only improve the global performance of video coding, but also provide great flexibility in complexity regulation.     

基于SSE技术的H．264运动估计的并行处理

H．264标准是ITU—T视频编码专家组（VcEG）和ISO／IECMPEG委员会正在制定的用于视频通信的新一代视频编码标准。运动估计是H．264最关键技术，占计算量的主要部分，因而成为视频压缩处理的瓶颈，因此必须研究运动估计的并行处理算法。通过介绍SSE技术的特点、数据结构和内联函数，在此基础上用SSE技术实现了运动估计并行算法。     

Blocking optimized SIMD tree search on modern processors

Tree search is a widely used fundamental algorithm. Modern processors provide tremendous computing power by integrating multiple cores, each with a vector processing unit. This paper reviews some studies on exploiting single instruction multiple date (SIMD) capacity of processors to improve the performance of tree search, and proposes several improvement methods on reported SIMD tree search algorithms. Based on blocking tree structure, blocking for memory alignment and dynamic blocking prefetch are proposed to optimize the overhead of memory access. Furthermore, as a way of non-linear loop unrolling, the search branch unwinding shows that the number of branches can exceed the data width of SIMD instructions in the SIMD search algorithm. The experiments suggest that blocking optimized SIMD tree search algorithm can achieve 1.6 times response speed faster than the un-optimized algorithm.     

A complexity-scalable software-based MPEG-2 video encoder

INTRODUCTION processors and digital signal processors (DSP), video encoding on these processors without hard- Digital video compression techniques have ware assistance may be an alternative with advan-played an important role in the field of telecom- tages of short development cycles, easy upgrademunication and multimedia systems where band- and low cost. Video coding consumes much com-width and storage resources are limited. The prime putation time, and so, is a problem for real-timeimp…     

Novel algorithm for complex bit reversal: employing vector permutation and branch reduction methods

We present novel vector permutation and branch reduction methods to minimize the number of execution cycles for bit reversal algorithms. The new methods are applied to single instruction multiple data （SIMD） parallel implementation of complex data floating-point fast Fourier transform （FFT）. The number of operational clock cycles can be reduced by an average factor of 3.5 by using our vector permutation methods and by 1.1 by using our branch reduction methods, compared with conventional implementations. Experiments on MPC7448 （a well-known SIMD reduced instruction set computing processor） demonstrate that our optimal bit-reversal algorithm consistently takes fewer than two cycles per element in complex array operations.     

Efficient SIMD optimization for media processors

Single instruction multiple data （SIMD） instructions are often implemented in modem media processors. Although SIMD instructions are useful in multimedia applications, most compilers do not have good support for SIMD instructions. This paper focuses on SIMD instructions generation for media processors. We present an efficient code optimization approach that is integrated into a retargetable C compiler. SIMD instructions are generated by finding and combining the same operations in programs. Experimental results for the UltraSPARC VIS instruction set show that a speedup factor up to 2.639 is obtained.