An ASIC design for edge detection in real time |
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Institution: | 1. Department of Molecular and Cellular Parasitology, Graduate School of Medicine, Juntendo University, 2-1-1 Hongo, Bunkyo-ku, Tokyo 113-8421, Japan;2. Department of Parasitology, National Institute of Infectious Diseases, Toyama 1-23-1, Shinjuku-ku, Tokyo 162-8640, Japan |
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Abstract: | An ASIC design for image processing which can implement edge, line and point detection on a single VLSI chip in real time is reported here. The design is based on a set of orthogonal Chebyshev polynomial based operators and consists of a pipelined array of registers and adders with a simple and modular structure which is easily amenable to VLSI implementation. The design has been implemented using VTI design tools on a SUN workstation and the estimated overall chip size is 10.18 mm × 6.92 mm for 1.5 μm CMOS process utilizing about 84,000 transistors. Although the hardware requirements are relatively low, real time processing of a 512 × 512 pixel image can be realized at a clock rate of 8 MHz. |
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