| 基于FPGA的UART实现 |
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| 引用本文： | 张文,薛顺瑞. 基于FPGA的UART实现[J]. 内江师范学院学报, 2012, 27(10): 33-35 |
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| 作者姓名： | 张文 薛顺瑞 |
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| 作者单位： | 1. 内江师范学院工程技术学院,四川 内江,641100
2. 电子科技大学,四川 成都,611731 |
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| 基金项目： | 内江师范学院院级科研项目资助(10NJZ-3) |
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| 摘 要： | 利用嵌入式技术,使用FPGA实现了多路全双工串口.该系统在接收端和发送端前都加一个具有8个缓冲单元的FIFO,实现内部模块时钟与串口速率匹配,同时,发送波特率和接收波特率等参数能够根据需要来进行相应的配置,并在Altera公司的CycloneⅢ系列FPGA硬件平台进行验证实验结果,该设计完全符合串口通信标准.
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| 关 键 词： | FPGA 多路串口 全双工 异步通信 |
FPGA-Based Realization of UART |
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| ZHANG Wen , XUE Shun-rui. FPGA-Based Realization of UART[J]. Journal of Neijiang Teachers College, 2012, 27(10): 33-35 |
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| Authors: | ZHANG Wen XUE Shun-rui |
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| Affiliation: | 1.College of Engineering Technology,Neijiang Normal University,Neijiang,Sichuan 641100,China; 2.University of Electronic Science and Technology of China,Chengdu,Sichuan 611731,China) |
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| Abstract: | By aid of embedded technology,the Multi-channel full duplex serial port is realized by means of FPGA.This design has added an 8-buffer-cell FIFO in front of transmitting terminal and receiving terminal in order to achieve rate adaptation between the internal module clock and UART.Besides,the serial port baud rate can be set to cater for needs of different communication baud.The experimental results are subjected to verification on the hardware FPGA Cyclone III platform of the Altera Company,which finds the design fully UART compatible. |
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| Keywords: | FPGA multi-channel UART full duplex asynchronous communication |
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