A methodology for evaluating the performance of CISC computer systems under single and two-level cache environments |
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| Institution: | 1. Department of CSE, Faculty of Engineering and Technology, Annamalai University, Tamil Nadu, India;2. Department of CSE, Gudlavalleru Engineering College, Gudlavalleru, India;1. Department of Environment and Sustainability Sciences, University for Development Studies, Tamale, Ghana;2. Department of Civil Engineering, Kwame Nkrumah University of Science and Technology, Kumasi Ghana;3. Department of Computer Engineering, Kwame Nkrumah University of Science and Technology, Kumasi Ghana;4. Department of History, University of Cape Coast, Cape Coast, Ghana |
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| Abstract: | This paper presents a simulation methodology for evaluating the performance of CISC computers. The method is called Message Flow Technique (MFT). MFT has several advantages over Instruction Flow Technique (IFT) we presented in 1]. The proposed methodology is applied to a single and two-level cache CISC system using 80486 SX as a case study. It was found that with a single-level on-chip cache of size 8KB, the performance of the system is considerably limited by the service time of BIU (Bus Interface Unit). The average service time of BIU, per instruction, was found to be around 1.0135 microseconds for our Modified Gibson Mix (MGM). With a second-level external cache of sizes 16KB, 32KB, 64KB, and 128KB the average performance improvements were found to be 1.4%, 18.6%, 39% and 53% respectively. The methodology presented here is an efficient and easy to use tool that could help performance analysts in evaluating computer systems. |
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