| 基于高速CPLD的实时连续正弦运算模块设计与应用 |
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| 引用本文： | 朱静,王林高. 基于高速CPLD的实时连续正弦运算模块设计与应用[J]. 南通职业大学学报, 2001, 15(3): 27-31 |
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| 作者姓名： | 朱静 王林高 |
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| 作者单位： | 1. 淮安纺织工业学校,江苏,淮安,223001
2. 淮阴工学院,江苏,淮安,223001 |
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| 摘 要： | 针对直接数字频率合成的相位截尾误差，提出了采用高速CPLD设计实时连续正弦运算模块彻底避免相位截尾误差问题，给出了几种可行的算法分析和谱纯度仿真讨论。该模块具有较好的输出信号质量，运行速度与DDFS相当，不仅可以和单片机构成两片结构的信号发生器，也可以作为信号源嵌入到各种片上电子系统设计中去，具有设计的灵活性和底层可重用性。
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| 关 键 词： | CPLD DDFS 正弦信号源 运算模块 两片式信号发生器 设计 信号输出 相位截止误差 |
| 文章编号： | 1008-5327(2001)03-0027-05 |
The Design and Application of Real-time Sine Module with High-speed CPLD |
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| ZHU Jin,WANG Lin-gao. The Design and Application of Real-time Sine Module with High-speed CPLD[J]. Journal of Nantong Vocational College, 2001, 15(3): 27-31 |
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| Authors: | ZHU Jin WANG Lin-gao |
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| Affiliation: | ZHU Jin WANG Lin-gao |
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| Abstract: | This paper puts forward a real-time sine module based on high-speed CPLD to avoid phase-cut-error of DDFS. The analysis of some feasible algorithms and emulations of iutput spectrum are also given in this paper. The output quality of this module is good with a speed corresponding to the speed of DDFS. Not only can this be used to constitute a 2-chip intellectualized sine-signal generator, but also used as a signal source to be embedded into various one-chip systems. |
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| Keywords: | CPLD DDFS sine signal source sine module |
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