RS(255,239)解码器并行钱氏搜索电路的面积优化

提出了一个全局优化算法(GOA)对RS(255,239)解码器中的并行钱氏搜索电路进行面积优化.通过查找钱氏搜索电路中GF (Galois field)常数乘法器的公共模2加运算并进行预运算,GOA能够有效地减少电路中异或门的数量,从而减少电路面积.与原有局部优化方法不同,GOA是一个全局优化算法.当每次迭代中同时有多个最大匹配对时,GOA通过选取与其他匹配对关系最小的一对作为最优匹配而不是随机地选择一对,使得当前结果对最终的优化结果影响最小.进一步将基于组的GOA用于GF乘法器组的优化,结果显示相对于直接实现方法,可使并行钱氏搜索电路的面积减少51%,而对GF乘法器的单独优化也能使电路面积减少26%.该优化方法可广泛地用于含有大量模2加运算的并行结构中.

Area optimization of parallel Chien search architecture for Reed-Solomon(255,239) decoder

A global optimization algorithm (GOA) for parallel Chien search circuit in Reed-Solomon (RS)(255,239) decoder is presented.By finding out the common modulo 2 additions within groups of Galois field (GF) multipliers and pre-computing the common items,the GOA can reduce the number of XOR gates efficiently and thus reduce the circuit area.Different from other local optimization algorithms, the GOA is a global one.When there are more than one maximum matches at a time,the best match choice in the GOA has the least impact on the final result by only choosing the pair with the smallest relational value instead of choosing a pair randomly.The results show that the area of parallel Chien search circuits can be reduced by 51% compared to the direct implementation when the group-based GOA is used for GF multipliers and by 26% if applying the GOA to GF multipliers separately.This optimization scheme can be widely used in general parallel architecture in which many GF multipliers are involved.