| 时序逻辑电路设计方法浅析 |
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| 引用本文： | 贺敬凯.时序逻辑电路设计方法浅析[J].深圳信息职业技术学院学报,2009,7(2):74-77. |
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| 作者姓名： | 贺敬凯 |
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| 作者单位： | 深圳信息职业技术学院电子通信技术系,深圳,518029 |
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| 摘 要： | 本文简要介绍了状态机理论以及时序逻辑电路的特点，给出了一种时序逻辑电路的设计模型，在此基础上将时序逻辑的设计问题转化为组合逻辑的设计问题。本文给出的时序电路模型将状态机的理论和技术应用其中，并可借助于EDA软件进行设计和仿真。本文提出的设计方法简洁实用，可用于数字电路课程时序电路部分的教学。
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| 关 键 词： | 有限状态机 时序逻辑设计 电子设计自动化 硬件描述语言 |
Analyses on design method for sequential logic circuits |
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| HE Jingkai.Analyses on design method for sequential logic circuits[J].Journal of Shenzhen Institute of Information Technology,2009,7(2):74-77. |
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| Authors: | HE Jingkai |
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| Institution: | HE Jingkai ( Department of Electronic Communications, Shenzhen Institute of Information Technology, Shenzhen 518029, China) |
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| Abstract: | The state machine theory and the characteristic of sequence logic circuit are introduced to form a sequential logic circuit design model based on which the sequential logic design is changed into combinational logic design. The mentioned model with the help of state machine theory can be simulated with EDA software. The design method is compact and can be used in lectures of sequential logic design part of digital circuit. |
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| Keywords: | finite state machine sequential logic design EDA HDL |
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