一种用于TLC闪存的速率兼容LDPC码

TLC闪存存储单元随着擦写次数不断增加，错误概率快速增大。基于TLC闪存信道结构，利用原模图LDPC码字扩展以及变量节点与TLC闪存存储页匹配关系，提出了一种速率兼容原模图LDPC码，所设计的速率兼容原模图LDPC码在保持信息位长度相同情况下，可实现可变码率，能够适应TLC闪存擦除次数增多而导致的不同纠错能力需求情况，编译码时只需一对LDPC编码器/译码器即可灵活处理所有码率，从而提高编码器/译码器的硬件利用率。仿真结果表明，所提出的速率兼容原模图LDPC码优于未经过逻辑页匹配的速率兼容原模图LDPC码，当误码率为[10-4]、码率分别为0.90、0.82、0.75时，所提出的速率兼容原模图LDPC码信噪比性能比基于PEG算法的非规则LDPC码均提高0.2dB以上。

A Rate Compatible LDPC Code for TLC Flash Memory

As the number of erasing and writing of TLC flash memory cells increases， the probability of error increases rapidly. Based on the TLC flash channel structure， this paper proposes a rate-compatible original mode LDPC code by using the original mode LDPC codeword extension and the matching relationship between the variable node and the TLC flash memory page. The designed rate compatible original mode LDPC code is maintained. When the information bit length is the same， the variable bit rate can be realized， which can adapt to different error correction capability requirements caused by the increased number of TLC flash erasures. Only a pair of LDPC encoders/decoders can be used to compile the code. Processing all code rates increases the hardware utilization of the encoder/decoder. The simulation results show that the proposed rate-compatible original mode LDPC code is better than the original mode LDPC code without logical page matching. When the bit error rate and code rate are 0.90， 0.82， and 0.75， respectively， the proposed rate is compatible. The SNR performance of the original pattern LDPC code is 0.2dB higher than that of the LDP algorithm based on the PEG algorithm.