| 宽带数字接收机中的超高速实时信号处理 |
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| 引用本文： | 胡亚,吴嗣亮. 宽带数字接收机中的超高速实时信号处理[J]. 科技通报, 2012, 28(2): 69-73 |
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| 作者姓名： | 胡亚 吴嗣亮 |
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| 作者单位： | 1. 北京理工大学信息与电子学院,北京100081;中国电科集团第五十四研究所,河北石家庄050081
2. 北京理工大学信息与电子学院,北京,100081 |
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| 摘 要： | 飞速发展的宽带数字接收机技术的瓶颈是实现器件的低速处理能力不能适应超高速ADC产生的超高速数据速率,常用的基于多相滤波的数字信道化方法和数字下变频方法形成的较低数据速率不能适应对宽带信号的处理。本文提出了用多路并行的方式将大规模FPGA内相对丰富的资源在低速率下合并为超高速处理的方法。在现有的工作速率为500 MHz以下的FPGA器件上实现了4.8GHz的超高速混频和超高速滤波,可满足信号带宽500 MHz的实时处理需求。
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| 关 键 词： | 实时信号处理 宽带数字接收机 超高速 |
Ultra-High Speed Real-time Signal Processing in Wideband Digital Receivers |
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| HU Ya , WU Siliang. Ultra-High Speed Real-time Signal Processing in Wideband Digital Receivers[J]. Bulletin of Science and Technology, 2012, 28(2): 69-73 |
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| Authors: | HU Ya WU Siliang |
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| Affiliation: | 1(1.School of Information and Electronics,Beijing Inst.of Technology,Beijing 100081,China; 2.The 54th Research Institute of CETC,Shijiazhuang 05008,China) |
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| Abstract: | The bottleneck of the wideband digital receiver is the mismatch between the relatively low processing speed of the real-time devices and the ultra-high data rate generated by ultra-high speed analog-to-digital converters(ADC).The normal solution,digital channelization or frequency-guided digital down conversion based on poly-phase filtering,result into relatively low data-rate,which is not applicable to deal with wideband signal.A multiple paralleled scheme is proposed to unite the relatively abundant resources in large-scale FPGA to achieve ultra-high processing.The ultra-high speed mixer and filter implementing on FPGA devices working at 300MHz can operate at 4.8GHz and satisfy the real-time processing requirement for signal with bandwidth up to 500MHz. |
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| Keywords: | real-time signal processing wideband digital receiver ultra-high speed |
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