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Formal verification |
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| Authors: | B Meenakshi |
| Institution: | (1) Department of Computer Sciences, University of Texas, Austin, University Station 1 MS C0500, 78712-0233 Austin, Texas, USA |
| Abstract: | This is a short tutorial on formal methods which are techniques for specifying and verifying complex software and hardware systems. A few examples of successful industrial use of these are also presented. |
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