| 工程实践中中规模组合逻辑电路设计的改进 |
| |
| 引用本文： | 洪少春. 工程实践中中规模组合逻辑电路设计的改进[J]. 泉州师范学院学报, 2004, 22(4): 31-35 |
| |
| 作者姓名： | 洪少春 |
| |
| 作者单位： | 泉州师范学院,高等职业技术学院,福建,泉州,362000 |
| |
| 摘 要： | 在工程实践中利用中规模集成电路设计组合逻辑电路需要在设计理念和方法上做一定的改进，以适应工程设计计算机化和工程实际的要求．章就此进行一定的探索，并就工程中应用较多的数据选择器、译码器及EPROM等来实现组合逻辑设计提出改进方法。
|
| 关 键 词： | 工程 中规模 组合逻辑 改进 |
| 文章编号： | 1009-8224(2004)04-0031-05 |
| 修稿时间： | 2004-04-23 |
Design with Mid-scale Integrate Circuit to Improve the Combined Logical Circuit in Engineering |
| |
| HONG Shao-Chun. Design with Mid-scale Integrate Circuit to Improve the Combined Logical Circuit in Engineering[J]. Journal of Quanzhou Normal College, 2004, 22(4): 31-35 |
| |
| Authors: | HONG Shao-Chun |
| |
| Abstract: | It needs to have new ideas and ways in design to use Mid-scale integrate circuit to improve the Combined Logical Circuit in engineering to meet the requirements of computerizing engineering design .This article talks about this and explores the ways of data selcctor,dedcipheer and EpROM to improve the design of Combined Logical Circuit. |
| |
| Keywords: | engineer Mid-scale Combined Logical Circuit improve |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
