| 不恢复余数阵列除法器的FPGA实现 |
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| 引用本文： | 吉雪芸,朱有产.不恢复余数阵列除法器的FPGA实现[J].保定师专学报,2010(3):56-59. |
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| 作者姓名： | 吉雪芸 朱有产 |
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| 作者单位： | 华北电力大学信息与网络管理中心,河北保定071003 |
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| 摘 要： | 在研究不恢复余数法的算法基础上,阐述以可控加/减法器（CAS）为基本组成单元的阵列除法器的构造原理,并给出一个完整的定点小数补码除法逻辑图,最后提出一种基于现场可编程门阵列（Field-Programmable Gate Array,简称FPGA）的除法器的硬件实现方法.
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| 关 键 词： | CAS 不恢复余数法 并行除法 阵列除法器 FPGA |
FPGA Implementation About the Array Divider on the Addition and Subtraction Alternating Method |
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| Ji Xueyun,Zhu Youchan.FPGA Implementation About the Array Divider on the Addition and Subtraction Alternating Method[J].Journal of Baoding Teachers College,2010(3):56-59. |
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| Authors: | Ji Xueyun Zhu Youchan |
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| Institution: | (Center of Information and Network Management,North China Electric Power University,Baoding 071003,China) |
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| Abstract: | The paper based on the algorithm about addition and subtraction alternating method,described in order to CAS as the basic unit of the structure array divider principle,and gave a full complement of fixed-point decimal division logic diagram.Finally,the paper presented a FPGA-based hardware implementation of the divider. |
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| Keywords: | CAS addition and subtraction alternating method parallel division array divider FPGA |
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